1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and for example, relates to a method for fabricating a semiconductor device forming a porous low dielectric constant dielectric film.
2. Related Art
With increasingly more microscopic and faster semiconductor devices, a wiring structure is moving from a single layer to multiple layers and semiconductor devices having five layers or more of metallic wiring structures have been developed and manufactured. However, as semiconductor devices become still finer, problems of a so-called inter-wire parasitic capacity and a signal transmission delay due to wire resistance have arisen. Then, in recent years, a signal transmission delay resulting from a multi-layer wiring structure is increasingly affecting speedup of semiconductor devices and various steps have been taken as measures for preventing such a delay. The signal transmission delay can generally be obtained by a product of the above inter-wire parasitic capacity and wire resistance. Thus, particularly in recent years, there is a trend to replace a conventional aluminum (Al) alloy as a wiring material with copper (Cu) or a Cu alloy (hereinafter referred to as Cu together) with low resistance to achieve speedup of LSI by lowering wire resistance. Since it is difficult to apply a dry etching method, which is frequently used for forming Al alloy wires, to Cu for micro processing, a damascene process is mainly adopted for Cu, in which a Cu film is deposited on a dielectric film, or “an insulating film” to which groove processing has been provided and then the Cu film is removed except in portions where the Cu film is embedded in a groove by chemical-mechanical polishing (CMP) to form embedded wiring. The Cu film is generally formed, after forming a thin seed layer by a sputtering process or the like, into a laminated film having a thickness of several hundred nanometers by electrolytic plating. Further, when forming multi-layer Cu wiring, particularly a wiring formation method called a dual damascene structure can also be used. In this method, a dielectric film is deposited on lower layer wiring and predetermined via holes and trenches for upper layer wiring are formed, and then Cu to be wiring material is embedded in the via holes and trenches simultaneously and further unnecessary Cu in the upper layer is removed by CMP for planarization to form embedded wiring.
To reduce the inter-wire capacity, on the other hand, instead of a dielectric film by the chemical vapor deposition (CVD) process using conventional silicon oxide (SiO2), the use of a SiCO film by the CVD process and that of a so-called coating film or an organic resin (polymer) film having SiCO composition by a coating method as a low dielectric constant material insulating film (low-k film) having fine pores have been studied. While a SiO2 film has the relative dielectric constant of 3.9, particularly a low dielectric constant coating film is believed to be capable of lowering the relative dielectric constant up to about 2.0 and thus is currently intensively being studied. A SiCO film formed by the CVD process whose relative dielectric constant can similarly be lowered has been widely used in recent years. However, such dielectric films having lower dielectric constants pose, on the other hand, a problem of mechanically weaker film strength.
Here, a SiCO film by the coating method or CVD process is known to be damaged by etching when forming a via hole or trench or in processes such as plasma ashing for separating a mask for etching and cleaning by a chemical solution. For a SiCO film, organic components (C (carbon) components) in the film are affected during the above processes to form a Si—OH group, which is an adsorption site of moisture, on the surface of or in the film. Thus, there has been a problem of increased hygroscopicity of the film. Particularly if the SiCO film is formed with a porous structure, gases are more likely to penetrate because of pores in the film. Therefore, the film will be damaged in a wider range. Further, the inclusion of moisture increases the dielectric constant and also oxidizes metal wires in post process, particularly in a thermal operation, causing a failure leading to degradation of wiring reliability.
When forming a barrier metal of Ta or the like to prevent diffusion of Cu into the low-k film, the barrier metal may not be formable as a continuous film because of exposed pores existing in a low dielectric constant film on a formed trench wall or via hole side wall. In such a case, a failure phenomenon of diffusion of Cu from a Cu wiring portion into the low-k film will be caused in post process or when a semiconductor device is operating. Such a failure phenomenon will lead to a problem of causing an open failure of metal wiring in the end. Particularly, the barrier metal tends to be discontinuous on the side wall of a via hole to be a micro-hole. Therefore, a technology to close pores exposed on the surface has been studied.
Here, a technology to repair the Si—OH bond on a damaged low-k film surface to the Si—CH3 bond by exposing the low-k film surface to an HMDS gas has been disclosed (for example, Published Unexamined Japanese Patent Application No. 2002-353308). Besides, a technology to substitute a hydrophilic group for the Si—OH bond on a low-k film surface has been disclosed (for example, Published Unexamined Japanese Patent Application No. 2006-114719 or 2006-73799). However, pores exposed on the low-k film surface cannot be closed by these repair technologies. Moreover, with these repair technologies, mechanical strength of the low-k film is not sufficient.